SPIRIT: a highly robust combinational test generation algorithm

In this paper, an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. The authors propose a new data structure for the complete implication graph that increases the precision of implication process. Next, they examine approaches like a single-cone processing, single path-oriented propagation, and backward justification and show that they are efficient to improve robustness of TPG algorithms. Finally, the authors propose efficient techniques and heuristics for these approaches. The resultant automatic test pattern generation system, called SPIRIT (Satisfiability Problem Implementation for Redundancy Identification and Test generation), combines the flexibility of the SAT-based TPG algorithms with the efficiency of the structural TPG algorithms. Experimental results demonstrate the robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to achieve 100% fault efficiency for a large set of benchmark circuits in a reasonable amount of time.

[1]  Peter Muth,et al.  A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.

[2]  Kurt Antreich,et al.  IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Wilfried Daehn,et al.  Contest: a fast ATPG tool for very large combinational circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Vishwani D. Agrawal,et al.  A transitive closure algorithm for test generation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  John A. Waicukauski,et al.  ATPG for ultra-large structured designs , 1990, Proceedings. International Test Conference 1990.

[6]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Joao Marques-Silva,et al.  Algorithms for solving Boolean satisfiability in combinational circuits , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[8]  Dhiraj K. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

[9]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[10]  Janak H. Patel,et al.  New Techniques for Deterministic Test Pattern Generation , 1999, J. Electron. Test..

[11]  Hideo Fujiwara,et al.  A scheduling problem in test generation , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[12]  H. Fujiwara,et al.  A framework for low complexity static learning , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[13]  Hideo Fujiwara,et al.  Spirit: satisfiability problem implementation for redundancy identification and test generation , 2000, Proceedings of the Ninth Asian Test Symposium.

[14]  Mario H. Konijnenburg,et al.  Test pattern generation with restrictors , 1993, Proceedings of IEEE International Test Conference - (ITC).

[15]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[17]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[18]  Malgorzata Marek-Sadowska,et al.  Star test: the theory and its applications , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[20]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[22]  Malgorzata Marek-Sadowska,et al.  STAR-ATPG: a high speed test pattern generator for large scan designs , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[23]  Michael H. Schulz,et al.  Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  S. Hellebrand,et al.  Pattern generation for a deterministic BIST scheme , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[25]  Giovanni Squillero,et al.  RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..

[26]  Sandeep K. Gupta,et al.  Efficient BIST TPG design and test set compaction via input reduction , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Kurt Keutzer,et al.  Why is ATPG easy? , 1999, DAC '99.

[28]  Paul Tafertshofer,et al.  SAT based ATPG using fast justification and propagation in the implication graph , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[29]  Scott Davidson,et al.  ITC'99 Benchmark Circuits - Preliminary Results , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[30]  Randal E. Bryant,et al.  Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[31]  Mitsuo Teramoto A method for reducing the search space in test pattern generation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[32]  Hideo Fujiwara,et al.  A New Data Structure for Complete Implication Graph with Application for Static Learning , 2000 .

[33]  Peter Wohl,et al.  Test generation for ultra-large circuits using ATPG constraints and test-pattern templates , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[34]  Hideo Fujiwara,et al.  SPIRIT: a highly robust combinational test generation algorithm , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[35]  Yumi K. Tsuji,et al.  EVIDENCE FOR A SATISFIABILITY THRESHOLD FOR RANDOM 3CNF FORMULAS , 1992 .

[36]  Hideo Fujiwara,et al.  The Complexity of Fault Detection Problems for Combinational Logic Circuits , 1982, IEEE Transactions on Computers.

[37]  D. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 2003 .

[38]  Janusz Rajski,et al.  A method to calculate necessary assignments in algorithmic test pattern generation , 1990, Proceedings. International Test Conference 1990.

[39]  Kurt Antreich,et al.  A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization , 1995, ICCAD.

[40]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[41]  Kurt Antreich,et al.  A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[42]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[43]  Leendert M. Huisman,et al.  A small test generator for large designs , 1992, Proceedings International Test Conference 1992.

[44]  Hideo Fujiwara,et al.  A framework for low complexitgy static learning , 2001, DAC '01.

[45]  Elizabeth M. Rudnick,et al.  Static logic implication with application to redundancy identification , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).