The Integrated-Gate Dual Transistor (IGDT)

IGCTs (Integrated Gate-Commutated Thyristors) and IGBTs (Insulated-Gate Bipolar Transistors) are currently available with blocking voltages up to 6.5 kV. Both devices have inherently short switching times but are nevertheless frequency limited by their dynamic losses. 10 kV IGCTs have been shown to be useable up to about 5.5 kVDC and 400 Hz (1). It would thus seem that market needs for PWM (pulse width modulation) at about 1 kHz might not be satisfied above 3 kV DC, due to the inherent losses of the aforementioned bipolar devices. The fundamental barrier presented by the charge stored in the n- base of IGBTs and IGCTs must be reduced at turn-off without increasing conduction losses. The use of a second, anode-side gate (n-gate) to reduce the high plasma density at turn-off has already been described for conventional snubbered GTOs (2, 3) but the technique had, until recently, not been applied to a snubberless device such as the IGCT. This paper will show the overall loss reductions that can be obtained by adding a second gate to the IGCT. The two transistors of the regenerative pnp/npn pair, integrated into their low inductance housing (thus giving rise to the device designation "IGDT") will be shown to allow added freedom for series connection.