Debugging Scenarios from the Trenches

This chapter describes several real-world debugging scenarios. These are based more or less on real-world examples. Names and technical details have been changed to protect both the innocent and the guilty, and some details were left out, simplified, or altered simply due to the fallibility of human memory. This first example is based very loosely on a real-world scenario, with the differences mostly to avoid cluttering the description up with confusing detail. The software is structured so that the UART receive ISR receives an entire message and notifies the background code via a semaphore when a message is received. Input data is buffered in an 8-byte FIFO, implemented in software. The RTS output of the 16550 is used to control data flow from the host. The receive ISR clears RTS to stop transmission when the FIFO holds 8 bytes. The background code reenables the host when the FIFO drops to 4 bytes. It has been calculated that the software, although it might not process a message immediately when notified by the ISR, is able on average to keep up with the data rate.