Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (<inline-formula><tex-math notation="LaTeX">$8$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq1-2588725.gif"/></alternatives></inline-formula>-Kbytes up to <inline-formula> <tex-math notation="LaTeX">$128$</tex-math><alternatives><inline-graphic xlink:href="enachescu-ieq2-2588725.gif"/> </alternatives></inline-formula>-Kbytes) implemented in various technology nodes. The 3D NEMFET-CMOS hybrid dual-port memory is on the average <inline-formula><tex-math notation="LaTeX">$25$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq3-2588725.gif"/></alternatives></inline-formula> percent smaller and <inline-formula><tex-math notation="LaTeX">$8$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq4-2588725.gif"/></alternatives></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$95$</tex-math><alternatives><inline-graphic xlink:href="enachescu-ieq5-2588725.gif"/> </alternatives></inline-formula> percent larger in terms of footprint when compared to <inline-formula> <tex-math notation="LaTeX">$90$</tex-math><alternatives><inline-graphic xlink:href="enachescu-ieq6-2588725.gif"/> </alternatives></inline-formula>, and <inline-formula><tex-math notation="LaTeX">$45$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq7-2588725.gif"/></alternatives></inline-formula> nm CMOS implementations, respectively. The write access time is approximately <inline-formula><tex-math notation="LaTeX">$2\times$</tex-math> <alternatives><inline-graphic xlink:href="enachescu-ieq8-2588725.gif"/></alternatives></inline-formula> higher, as it is dominated by the mechanical movement of the NEMFET's suspended gate, while the read access time is about <inline-formula><tex-math notation="LaTeX">$12$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq9-2588725.gif"/></alternatives></inline-formula> percent lower, when compared with <inline-formula><tex-math notation="LaTeX">$45$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq10-2588725.gif"/></alternatives></inline-formula> nm CMOS counterparts. For small size memories our proposal results in at least <inline-formula><tex-math notation="LaTeX">$15$</tex-math> <alternatives><inline-graphic xlink:href="enachescu-ieq11-2588725.gif"/></alternatives></inline-formula> percent and <inline-formula><tex-math notation="LaTeX">$23$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq12-2588725.gif"/></alternatives></inline-formula> percent energy reductions for <inline-formula><tex-math notation="LaTeX">$100$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq13-2588725.gif"/></alternatives></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$50$</tex-math><alternatives><inline-graphic xlink:href="enachescu-ieq14-2588725.gif"/> </alternatives></inline-formula> percent data transition probability, respectively. For large size memories an energy reduction of about <inline-formula><tex-math notation="LaTeX">$40$</tex-math><alternatives> <inline-graphic xlink:href="enachescu-ieq15-2588725.gif"/></alternatives></inline-formula> percent was obtained, as in this case the static energy is predominant.

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