Analysis of NBTI-induced SNM degradation in power-gated SRAM cells

Temporal reliability degradation mechanism, and NBTI in particular, are especially critical for SRAM cells. In fact, unlike logic gates, which under some conditions can be forced into an NBTI-immune state, SRAM cells are always subject to aging, whatever value they are storing. In this work, we first quantify the aging, in terms of degradation of the signal-to-noise margin (SNM), of an SRAM cell as a function of the value stored in the cell, on a 45nm industrial technology. Then, we show how it is possible, by applying power gating to the memory cell, to further reduce the SNM degradation. Finally, we study the joint effect of power gating and bit control techniques.

[1]  Kaushik Roy,et al.  Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Luca Benini,et al.  Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology , 2007, GLSVLSI '07.

[3]  Eric Rotenberg,et al.  Adaptive mode control: A static-power-efficient cache design , 2003, TECS.

[4]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[5]  Enrico Macii,et al.  NBTI-aware power gating for concurrent leakage and aging optimization , 2009, ISLPED.

[6]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[7]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[8]  Yu Cao,et al.  Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[9]  Hao-I Yang,et al.  Impacts of NBTI on SRAM array with power gating structure , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[10]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[11]  D. Kwong,et al.  Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling , 2002, IEEE Electron Device Letters.

[12]  Luca Benini,et al.  Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints , 2008, 2008 Design, Automation and Test in Europe.

[13]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[14]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[15]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[16]  Muhammad Ashraful Alam,et al.  Reliability- and Process-variation aware design of integrated circuits — A broader perspective , 2008, 2011 International Reliability Physics Symposium.

[17]  Kaushik Roy,et al.  Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ , 2007, 2007 IEEE International Test Conference.

[18]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[19]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[20]  Koji Nii,et al.  A low power SRAM using auto-backgate-controlled MT-CMOS , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).