High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-/spl mu/m photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/. An extremely high input sensitivity of 15 mV/sub p-p/ and a wide phase margin of 260/spl deg/ at 10 Gb/s are achieved. >

[1]  P. M. Solomon,et al.  Bipolar transistor design for optimized power-delay logic circuits , 1979 .

[2]  Kazuo Hagimoto,et al.  13 Gb/s D-type flip-flop IC using GaS MESFETs , 1990 .

[3]  Hans-Martin Rein,et al.  3.8 Gbit/s bipolar master/slave D-flip-flop IC as a basic element for high-speed optical communication systems , 1986 .

[4]  M. Suzuki,et al.  10-Gbit/s GaAs MESFET IC's for ultra high-speed transmission systems , 1990, 12th Annual Symposium on Gallium Arsenide Integrated Circuit (GaAs IC).

[5]  J. Hauenschild,et al.  A silicon bipolar decision circuit operating up to 15 Gb/s , 1991 .

[6]  Hiroshi Hamano,et al.  10 Gbit/s optical front end using Si-bipolar preamplifier IC, flipchip APD, and slant-end fibre , 1991 .

[7]  J. Hauenschild,et al.  Suitability of present silicon bipolar IC technologies for optical fibre transmission rates around and above 10 Gbit/s , 1990 .

[8]  Osaake Nakajima,et al.  Twenty-Gbit/s signal transmission using a simple high-sensitivity optical receiver , 1992 .

[9]  M. Soda,et al.  A Si bipolar chip set for 10 Gb/s optical receiver , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[10]  Noboru Ishihara,et al.  9 GHz bandwidth, 8-20 dB controllable-gain monolithic amplifier using AlGaAs/GaAs HBT technology , 1989 .

[11]  J. Hauenschild,et al.  A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology , 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

[12]  H. Ichino,et al.  18-GHz 1/8 dynamic frequency divider using Si bipolar technologies , 1989 .

[13]  Y. Amemiya,et al.  A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation , 1987 .

[14]  S. Konaka,et al.  HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter , 1990, International Technical Digest on Electron Devices.

[15]  H. Ichino,et al.  A 10 Gb/s decision circuit using AlGaAs/GaAs HBT technology , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[16]  Yutaka Miyamoto,et al.  Over 10 Gb/s Regenarators Using Monolithic IC's for Lightwave Communication Systems , 1991, IEEE J. Sel. Areas Commun..