Low-power CMOS at Vdd = 4kT/q

Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic.

[1]  Allen M. Peterson,et al.  Energy considerations in multichip-module based multiprocessors , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  J. Burr,et al.  Cryogenic ultra low power CMOS , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

[3]  Kaushik Roy,et al.  Ultra-low power digital subthreshold logic circuits , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).