A ParallelArchitecture forDiscrete Relaxation Algointhm

Discrete relaxation techniques haveproven useful insolv- ingawiderangeofproblems indigital signal anddigital imagepro- cessing, artificial intelligence, operations research, andmachine vi- sion. Muchworkhasbeendevoted tofinding efficient hardware architectures. Thispapershowsthataconventional hardware design foraDiscrete Relaxation Algorithm (DRA)suffers from0(n2m3) time complexity and0(n2m2) spacecomplexity. Byreformulating DRA into aparallel computational treeandusing amultiple tree-root pipelining scheme, timecomplexity isreduced to0(nm),while thespacecom- plexity isreduced byafactor of2.Forcertain relaxation processing, thespacecomplexity canevenbedecreased to0(nm).Furthermore, atechnique fordynamic configuring anarchitectural wavefront isused whichleads toan0(n)timehighly concurrent DRA3architecture. IndexTerms-Algorithm-configured dynamic architectural wave- front system, associative circular pipelining, Discrete Relaxation Al- gorithm (DRA), interleaved processing, multiprocessor architecture, recursive systolic computation, VLSI.