Fault simulation for multiple faults using shared BDD representation of fault sets

The authors propose a novel fault simulation technique for multiple faults. In order to handle a large number of multiple faults, sets of multiple faults are represented by Boolean functions, in which shared binary decision diagrams (BDDs) are used as an internal representation of Boolean functions. The authors also propose a fault dropping method, prime fault dropping, which is used efficiently to execute multiple fault simulation. The authors have succeeded in simulating 39 million double faults of a circuit of 2300 gates with about 20 Mbyte storage.<<ETX>>

[1]  Randal E. Bryant,et al.  Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Melvin A. Breuer,et al.  Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis , 1982, IEEE Transactions on Computers.

[3]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[4]  Joseph L. A. Hughes Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Nagisa Ishiura,et al.  Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.

[7]  Janusz Rajski,et al.  A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Edward J. McCluskey,et al.  The critical path for multiple faults , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.