Enhancing the Unified Logical Effort algorithm for branching and load distribution

In this paper, the authors proposed a novel technique to calculate the capacitance distribution and branching effort of a multiple fan-out logic path for equal propagation delay in each path regardless of number of gates and lengths of the wire segments in those logic path. The authors utilize the prior methods for the Unified Logical Effort (ULE) methodology as the basis of delay estimation and transistor sizing for the work of this paper. The runtime for fan-out of 2 is logarithmic in n or O(log2(n)), where n is the precision index. Several examples are also analyzed and detailed using the proposed algorithm showing how the branching effort can easily be calculated in the presence of a complex circuit tree with arbitrary loading.