A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier

A low power, high PSRR, clock-free, current-controlled class-D audio power amplifier is presented. The proposed audio amplifier utilizes integral sliding mode control (ISMC) to ensure robust operation and to minimize the steady-state error. This architecture has two feedback loops: an outer voltage loop that minimizes the voltage error between the input and output audio signals, and an inner current loop that measures the inductor current to track the input signal accurately. The proposed amplifier achieves up to 82 dB of power supply rejection ratio (PSRR), more than 90 dB of signal-to-noise (SNR) ratio over the entire audio band, and total harmonic distortion plus noise (THD+N) as low as 0.02%. A power-supply-induced intermodulation distortion (PS-IMD) of approximately - 90 dBc was measured for an input voltage signal of 2 Vpp at 1 kHz and a sinusoidal power-supply ripple of 300 mVpp at 217 Hz superimposed on the DC level. The IC prototype's controller consumes 30% less power than those of recently published works. The audio amplifier operates with a 2.7-V single voltage supply and delivers a maximum output power of 410 mW with 84% peak efficiency (η) into an 8 Ω speaker. It was fabricated using 0.5 μm CMOS standard technology, and occupies a total active area of 1.65 mm2.

[1]  Edgar Sánchez-Sinencio,et al.  Low-Power High-Efficiency Class D Audio Power Amplifiers , 2009, IEEE Journal of Solid-State Circuits.

[2]  Luis García de Vicuña,et al.  Current distribution control design for paralleled DC/DC converters using sliding-mode control , 2004, IEEE Transactions on Industrial Electronics.

[3]  Hao-Chi Chang,et al.  Sliding mode control on electro-mechanical systems , 1999 .

[4]  D. J. Pagano,et al.  Sliding bifurcations of equilibria in planar variable structure systems , 2003 .

[5]  J. S. Chang,et al.  Analysis and design of power efficient class D amplifier output stages , 2000 .

[6]  Ali H. Nayfeh,et al.  Robust control of parallel DC-DC buck converters by combining integral-variable-structure and multiple-sliding-surface control schemes , 2002 .

[7]  Joseph Sylvester Chang,et al.  Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Joseph Sylvester Chang,et al.  Filterless class D amplifiers: power-efficiency and power dissipation , 2010, IET Circuits Devices Syst..

[9]  Y.M. Lai,et al.  On the practical design of a sliding mode voltage controlled buck converter , 2005, IEEE Transactions on Power Electronics.

[10]  E. Gaalaas,et al.  Integrated stereo delta-sigma class D amplifier , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[11]  Bah-Hwee Gwee,et al.  An investigation into the parameters affecting total harmonic distortion in low-voltage low-power Class-D amplifiers , 2003 .

[12]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[13]  Sudip K. Mazumder,et al.  Design and experimental validation of a multiphase VRM controller , 2005 .

[14]  Edgar Sánchez-Sinencio,et al.  A 470μW clock-free current-controlled class D amplifier with 0.02% THD+N and 82dB PSRR , 2010, 2010 Proceedings of ESSCIRC.

[15]  Edgar Sánchez-Sinencio,et al.  Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback , 2007, IEEE Transactions on Consumer Electronics.

[16]  Joseph Sylvester Chang,et al.  THD of Closed-Loop Analog PWM Class-D Amplifiers , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  G. Burra,et al.  A 700+-mW class D design with direct battery hookup in a 90-nm process , 2005, IEEE Journal of Solid-State Circuits.

[18]  Chung-Wei Lin,et al.  A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[19]  Edgar Sánchez-Sinencio,et al.  Two Class-D audio amplifiers with 89/90% efficiency and 0.02/0.03% THD+N consuming less than 1mW of quiescent power , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[20]  Ranjit Gharpurey,et al.  A self oscillating class D audio amplifier with 0.0012% THD+N and 116.5 dB dynamic range , 2010, IEEE Custom Integrated Circuits Conference 2010.

[21]  G.A. Rincon-Mora,et al.  Current-sensing techniques for DC-DC converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[22]  C. Gendarme,et al.  CMOS Circuit Design, Layout, and Simulation, 2nd edition [Book Review] , 2006, IEEE Circuits and Devices Magazine.

[23]  Josep M. Guerrero,et al.  Design of voltage-mode hysteretic controllers for synchronous buck converters supplying microprocessor loads , 2005 .