Circuit simulation of workload-dependent RTN and BTI based on trap kinetics

A simulation methodology is presented capable of evaluating the transient impact of trap kinetics in transistors at the circuit level and thus the effects caused by them, particularly Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI). The downscaling of channel area leads to transistors with a smaller number of traps, but each trap causing a larger impact on the transistor’s electrical parameters, increasing its importance in circuit reliability. Despite the increasing impact of these effects on circuit reliability there are still no Computer-Aided Design (CAD) tools capable of analyzing the trapping kinetics and the methodologies presented in the literature suffer from either lack of computational efficiency or accuracy. This paper presents a comprehensive trap simulation methodology relying on both theoretical evaluations and experimental device characterization. The developed simulation framework performs a transient SPICE simulation on an arbitrary design considering the trap activity in situ, allowing accurate simulations of both RTN and BTI effects, at DC, AC or arbitrarily changing bias conditions. In order to perform statistical simulations, the simulation framework may be run inside a Monte Carlo loop. Case studies on a SRAM and on a ring oscillator are performed considering the workload dependence and the BTI effect during the simulation.