Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low VDD. Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when VDD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low VDD.

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