Performance of a partitioned broadband antenna array processor using convolution constraints

Implementation of a time domain element space processor for a broadband antenna array using a partitioned processor is achieved by forming a fixed beam of specified frequency response in the look direction and a set of auxiliary beams. The weights of these beams are adjusted to remove the undesired directional interferences from the main beam. This paper discusses a set of constraints referred to as convolution constraints for the auxiliary beams and evaluates the performance of the processor to show that the processor with the proposed design is computationally efficient, robust against steering delay errors and does not require pre-steering.