论文信息 - Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

We report a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths. Thanks to an original extraction method and low temperature measurements, we demonstrate that the mobility behaviour is deeply impacted by the down-scaling because of Coulomb scattering. Introducing this behaviour into a saturation current model, we clearly explain the I/sub ON/ enhancement trend of all strained devices.

[1] C.G. Sodini,et al. The effect of high fields on MOS device and circuit performance , 1984, IEEE Transactions on Electron Devices.

[2] K. Rim,et al. Fabrication and analysis of deep submicron strained-Si n-MOSFET's , 2000 .

[3] D. Antoniadis,et al. Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress , 2001, IEEE Electron Device Letters.

[4] Jung-Suk Goo,et al. Scalability of strained-Si nMOSFETs down to 25 nm gate length , 2003, IEEE Electron Device Letters.

[5] G. Reimbold,et al. Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress , 2004, IEEE Transactions on Electron Devices.

[6] R. Chau,et al. A 90-nm logic technology featuring strained-silicon , 2004, IEEE Transactions on Electron Devices.

[7] G. Ghibaudo,et al. Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs , 2004, IEEE Electron Device Letters.