An efficient, low-cost I/O subsystem for network processors

An efficient I/O subsystem enables cost-effective network processing. To improve high-speed data transfer, the I/O subsystem sends data directly into the processing core's register file. An implementation of this subsystem in a single-chip network processor , the Pro/sup 3/, can sustain advanced inspection firewall processing of 2.5-Gbps TCP traffic.

[1]  N. Zervos,et al.  Application decomposition for high-speed network processing platforms , 2002, 2nd European Conference on Universal Multiservice Networks. ECUMN'2001 (Cat. No.02EX563).

[2]  N. Cravotta.  NETWORK PROCESSORS : THE SKY'S THE LIMIT , 1999 .

[3]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[4]  Andrew R. Pleszkun,et al.  Implementation of the PIPE processor , 1991, Computer.

[5]  H. T. Kung,et al.  Supporting systolic and memory communication in iWarp , 1990, ISCA '90.

[6]  Diederik Verkest,et al.  A novel architecture for efficient protocol processing in high speed communication environments , 2000, 1st European Conference on Universal Multiservice Networks. ECUMN'2000 (Cat. No.00EX423).