Fault simulation in a distributed environment

Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>

[1]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[2]  P. R. Menon,et al.  Fault-simulation methods — extensions and comparison , 1981, The Bell System Technical Journal.

[3]  Prabhakar Goel.  Test generation costs analysis and projections , 1980, DAC '80.

[4]  Gregory F. Pfister,et al.  The Yorktown Simulation Engine: Introduction , 1982, 19th Design Automation Conference.

[5]  David Lee,et al.  A distributed processing system for naval data communication networks , 1899, AFIPS National Computer Conference.

[6]  Oscar H. Ibarra,et al.  Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.

[7]  Daniel A. Reed,et al.  Stencils and Problem Partitionings: Their Influence on the Performance of Multiple Processor Systems , 1987, IEEE Transactions on Computers.

[8]  J. D. Stauffer,et al.  Part II: Logic circuit simulation , 1979, IEEE Circuits & Systems Magazine.

[9]  Gregory Francis Pfister,et al.  The Yorktown Simulation Engine: Introduction , 1982, DAC 1982.

[10]  Wesley W. Chu,et al.  Estimation of Intermodule Communication (IMC) and Its Applications in Distributed Processing Systems , 1984, IEEE Transactions on Computers.

[11]  E. Schmidt,et al.  Lex—a lexical analyzer generator , 1990 .

[12]  Jacob A. Abraham,et al.  Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[14]  Zarka Cvetanovic,et al.  The Effects of Problem Partitioning, Allocation, and Granularity on the Performance of Multiple-Processor Systems , 1987, IEEE Transactions on Computers.

[15]  Parker,et al.  Design for Testability—A Survey , 1982, IEEE Transactions on Computers.

[16]  Hideo Fujiwara,et al.  The Complexity of Fault Detection Problems for Combinational Logic Circuits , 1982, IEEE Transactions on Computers.

[17]  Nobuhiko Koike,et al.  HAL; A Block Level Hardware Logic Simulator , 1983, 20th Design Automation Conference Proceedings.

[18]  Murray Hill,et al.  Yacc: Yet Another Compiler-Compiler , 1978 .

[19]  P. Goel.  Test Generation Costs Analysis and Projections , 1980, 17th Design Automation Conference.

[20]  Jacob A. Abraham,et al.  CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator , 1985, ITC.