Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes

Single event transient (SET) pulse widths produced from heavy ion irradiation in digital ICs are measured using a variable-delay temporal-latch test structure. We show for the first time that there is a wide distribution of SET pulse widths created by heavy ion radiation in digital CMOS logic at given linear energy transfer (LET) levels. We were able to measure SET pulse widths from as short as 344 ps to greater than 1.5 ns in 0.18 /spl mu/m CMOS technology at LETs greater than 80 MeV-cm /sup 2//mg. Depending on LET, the cross section of the very long SET pulses were as much as four orders of magnitude smaller than for the shorter pulse widths. This has substantial implications for hardening techniques; specifically, we now know that we can dramatically improve the SET hardness without suffering the speed penalties required to remove the longest transients.

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