A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications

A 14-bit, 320MSPS digital-to-analog converter is designed for high-speed applications. Considering the trade-off among linearity, dynamic performance, chip area, and power dissipation, the proposed DAC employs 5+4+5 segmented structure. The paper focuses on the design of several key circuits, and presents the experiment results (DNL=plusmn2.0LSB , INL=plusmn2.7LSB , SFDR=72.6dB @ fdata=320MSPS, fout= 4.375 MHz) based on the SMIC 0.35 mum mixed signal 2P3M CMOS process model. The chip has been fabricated in the SMIC 3.3 V technology with an active area of 2.6times2.6 mm2.

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