Survey of noise performances and scaling effects in deep submicron CMOS devices from different foundries

Submicron CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25 and 0.18 mum technologies from different foundries. This allows to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicron CMOS processes.

[1]  R. Castello,et al.  Experimental study and modeling of the white noise sources in submicron Pand N-MOSFETs , 2001 .

[2]  Willy Sansen,et al.  Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip , 2000 .

[3]  Kenneth R. Laker,et al.  Design of analog integrated circuits and systems , 1994 .

[4]  Massimo Manghisoni,et al.  Submicron CMOS technologies for low-noise analog front-end circuits , 2002 .

[5]  G. De Geronimo,et al.  MOSFET optimization in deep submicron technology for charge amplifiers , 2005, IEEE Transactions on Nuclear Science.

[6]  Federico Faccio,et al.  Noise characterization of a CMOS technology for the LHC experiments , 2001 .

[7]  A. Marchioro,et al.  A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments , 2004, IEEE Transactions on Nuclear Science.

[8]  L. Fabris,et al.  Optimization of front-end design in imaging and spectrometry applications with room temperature semiconductor detectors , 2001, 2001 IEEE Nuclear Science Symposium Conference Record (Cat. No.01CH37310).

[9]  P. O'Connor,et al.  Amplitude and time measurement ASIC with analog derandomization , 2002, 2002 IEEE Nuclear Science Symposium Conference Record.

[10]  L. Ratti,et al.  Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers , 2001, 2001 IEEE Nuclear Science Symposium Conference Record (Cat. No.01CH37310).

[11]  Federico Faccio,et al.  Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects , 1999 .

[12]  Charles G. Sodini,et al.  A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon , 1989 .

[13]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[14]  P. O'Connor,et al.  Front-end electronics for the RatCAP mobile animal PET scanner , 2004, IEEE Transactions on Nuclear Science.

[15]  G. Geronimo,et al.  Amplitude and time measurement ASIC with analog derandomization , 2003 .

[16]  A. Ziel.  Noise in solid state devices and circuits , 1986 .

[17]  K. Yeo,et al.  Effect of technology scaling on the 1/f noise of deep submicron PMOS transistors , 2004 .

[18]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[19]  Massimo Manghisoni,et al.  Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors , 2003 .

[20]  R. J. Yarema,et al.  FPIX2: a radiation-hard pixel readout chip for BTeV , 2001 .