Enhance GCC loop optimizations in multicore context

Multicore and multiprocessor based solutions are nowadays on an ascending path; the software tool-chain should keep the pace and design solutions that lead to the best use of the hardware. Cache memory is one hardware component, which evolved in the multicore context. Even so, the current cache designs have limitations that can be transformed into optimization opportunities on the compiler side. This paper proposes a solution to improve the cache usage by performing complex loop optimizations in the compiler, enhancing data locality and parallelism.