Features supporting system-level specification in HDLs

As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<<ETX>>

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