Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

[1]  M. Yakimov,et al.  Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer , 2006 .

[2]  Tahir Ghani,et al.  Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[3]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[4]  E. Vogel,et al.  Half-cycle atomic layer deposition reaction studies of Al2O3 on (NH4)2S passivated GaAs(100) surfaces , 2008 .

[5]  D. Webb,et al.  Inversion mode n-channel GaAs field effect transistor with high-k/metal gate , 2008 .

[6]  Suman Datta,et al.  High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .

[7]  Yanning Sun,et al.  Scaling of In0.7Ga0.3As buried-channel MOSFETs , 2008, 2008 IEEE International Electron Devices Meeting.

[8]  E. Vogel,et al.  Half-cycle atomic layer deposition reaction studies of Al2O3 on In0.2Ga0.8As (100) surfaces , 2008 .

[9]  Yasuyuki Miyamoto,et al.  High drain current (>2A/mm) InGaAs channel MOSFET at VD=0.5V with shrinkage of channel length by InP anisotropic etching , 2011, 2011 International Electron Devices Meeting.

[10]  Ming Zhu,et al.  Silane–Ammonia Surface Passivation for Gallium Arsenide Surface-Channel n-MOSFETs , 2009, IEEE Electron Device Letters.

[11]  下村 浩 A study on high-frequency performance in MOSFETs scaling , 2011 .

[12]  Peide D. Ye,et al.  Size-Dependent-Transport Study of $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ Gate-All-Around Nanowire MOSFETs: Impact of Quantum Confinement and Volume Inversion , 2012, IEEE Electron Device Letters.

[13]  Jack C. Lee,et al.  Effects of gate-first and gate-last process on interface quality of In0.53Ga0.47As metal-oxide-semiconductor capacitors using atomic-layer-deposited Al2O3 and HfO2 oxides , 2009 .

[14]  T. Shen,et al.  High-performance surface channel In-rich In0.75Ga0.25As MOSFETs with ALD high-k as gate dielectric , 2008, 2008 IEEE International Electron Devices Meeting.

[15]  A. Lacaita,et al.  Reliable extraction of MOS interface traps from low-frequency CV measurements , 1998, IEEE Electron Device Letters.

[16]  P. Ye,et al.  Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors , 2011 .

[17]  Farhad Larki,et al.  Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography , 2012, Nanoscale Research Letters.

[18]  Kazuo Terada,et al.  Comparison of MOSFET-threshold-voltage extraction methods , 2001 .

[19]  Insoo Woo,et al.  Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET , 2008 .

[20]  G. Lo,et al.  Inversion-Mode Self-Aligned $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor With HfAlO Gate Dielectric and TaN Metal Gate , 2008, IEEE Electron Device Letters.

[21]  Juin J. Liou,et al.  A review of recent MOSFET threshold voltage extraction methods , 2002, Microelectron. Reliab..

[22]  J. Kavalieros,et al.  High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.

[23]  S. Sze,et al.  Physics of Semiconductor Devices: Sze/Physics , 2006 .

[24]  Peide D. Ye,et al.  Size-Dependent-Transport Study of In 0 . 53 Ga 0 . 47 As Gate-All-Around Nanowire MOSFETs : Impact of Quantum Confinement and Volume Inversion , 2012 .

[25]  Krishna C. Saraswat,et al.  Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals , 2010 .

[26]  P. Ye,et al.  High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm , 2008, IEEE Electron Device Letters.

[27]  Jun Luo,et al.  Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status , 2011 .

[28]  Navakanta Bhat,et al.  Performance and variability trade-off with gate-to-source/drain overlap length , 2012 .

[29]  Paul W. Leu,et al.  Nanoscale doping of InAs via sulfur monolayers , 2009 .

[30]  Juin J. Liou,et al.  Revisiting MOSFET threshold voltage extraction methods , 2013, Microelectron. Reliab..

[31]  Xiao Gong,et al.  Strained In0.53Ga0.47As n-MOSFETs: Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineering , 2006, 2009 Symposium on VLSI Technology.

[32]  P. D. Ye,et al.  High Performance Deep-Submicron Inversion-Mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/µm: New HBr pretreatment and channel engineering , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[33]  Minkyu Je,et al.  RF Characteristics of 0.18 um CMOS Transistors , 2002 .

[34]  Robert W. Dutton,et al.  Impact of lateral source/drain abruptness on device performance , 2002 .

[35]  G. Ghibaudo Critical MOSFETs operation for low voltage/low power IC's: ideal characteristics, parameter extraction, electrical noise and RTS fluctuations , 1997 .

[36]  H. Grubin The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[37]  Wilman Tsai,et al.  High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3∕Ga2O3(Gd2O3) as gate dielectrics , 2008 .

[38]  J. Champlain,et al.  High frequency capacitance-voltage technique for the extraction of interface trap density of the heterojunction capacitor: Terman’s method revised , 2011 .

[39]  B. Yang,et al.  Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET , 2008, IEEE Electron Device Letters.

[40]  High-Frequency Performance of Self-Aligned Gate-Last Surface Channel $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFET , 2012, IEEE Electron Device Letters.

[41]  J. Kwo,et al.  Advances in GaAs Mosfet's Using Ga 2 O 3 (Gd 2 O 3 ) as Gate Oxide , 1999 .

[42]  S.K. Banerjee,et al.  Fabrication of Self-Aligned Enhancement-Mode $ \hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs With $ \hbox{TaN/HfO}_{2}\hbox{/AlN}$ Gate Stack , 2008, IEEE Electron Device Letters.

[43]  Y. J. Lee,et al.  Atomic-layer-deposited HfO$_{2}$ on In$_{0.53}$Ga$_{0.47}$As -- passivation and energy-band parameters , 2008 .

[44]  E. Lind,et al.  High-Frequency Performance of Self-Aligned Gate-Last Surface Channel MOSFET , 2012 .

[45]  Y. D. Wu,et al.  Self-aligned inversion-channel In0.75Ga0.25As metal–oxide–semiconductor field-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics , 2010 .