Safety-Assured Model-Driven Design of the Multifunction Vehicle Bus Controller

In this paper, we present a formal model-driven design approach to establish a safety-assured implementation of multifunction vehicle bus controller (MVBC), which controls the data transmission among the devices of the vehicle. First, the generic models and safety requirements described in International Electrotechnical Commission Standard 61375 are formalized as time automata and timed computation tree logic formulas, respectively. With model checking tool Uppaal, we verify whether or not the constructed timed automata satisfy the formulas and several logic inconsistencies in the original standard are detected and corrected. Then, we apply the code generation tool Times to generate C code from the verified model, which is later synthesized into a real MVBC chip, with some handwriting glue code. Furthermore, the runtime verification tool RMOR is applied on the integrated code, to verify some safety requirements that cannot be formalized on the timed automata. For evaluation, we compare the proposed approach with existing MVBC design methods, such as BeagleBone, Galsblock, and Simulink. Experiments show that more ambiguousness or bugs in the standard are detected during Uppaal verification, and the generated code of Times outperforms the C code generated by others in terms of the synthesized binary code size. The errors in the standard have been confirmed and the resulting MVBC has been deployed in the real train communication network.

[1]  Gwi-Tae Park,et al.  Performance evaluation and verification of communication protocol for railway signaling systems , 2005, Comput. Stand. Interfaces.

[2]  Panagiotis Louridas,et al.  Static code analysis , 2006, IEEE Software.

[3]  Joël Ouaknine,et al.  Model-Checking for Real-Time Systems , 1995, FCT.

[4]  Aloysius K. Mok,et al.  Safety analysis of timing properties in real-time systems , 1986, IEEE Transactions on Software Engineering.

[5]  Daniel Kroening,et al.  CBMC - C Bounded Model Checker - (Competition Contribution) , 2014, TACAS.

[6]  Gérard Berry SCADE: Synchronous Design and Validation of Embedded Control Software , 2007 .

[7]  Tao Tang,et al.  Energy-Efficient Communication-Based Train Control Systems With Packet Delay and Loss , 2016, IEEE Transactions on Intelligent Transportation Systems.

[8]  R. Aarthipriya,et al.  FPGA implementation of Multifunction Vehicle Bus Controller with Class 2 interface and verification using Beaglebone , 2015 .

[9]  Lui Sha,et al.  From Stateflow Simulation to Verified Implementation: A Verification Approach and A Real-Time Train Controller Design , 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[10]  Neeraj Suri,et al.  A Lease Based Hybrid Design Pattern for Proper-Temporal-Embedding of Wireless CPS Interlocking , 2015, IEEE Transactions on Parallel and Distributed Systems.

[11]  Tim Kelly,et al.  Safety tactics for software architecture design , 2004, Proceedings of the 28th Annual International Computer Software and Applications Conference, 2004. COMPSAC 2004..

[12]  J. Lazaro,et al.  A novel SoC architecture for a MVB slave node , 2008, 2008 34th Annual Conference of IEEE Industrial Electronics.

[13]  Klaus Havelund,et al.  Runtime Verification of C Programs , 2008, TestCom/FATES.

[14]  Jingjing Pei,et al.  Applying systems thinking approach to accident analysis in China: case study of "7.23" Yong-Tai-Wen High-Speed train accident , 2015 .

[15]  Yu Jiang,et al.  Design and optimization of multi-clocked embedded systems using formal technique , 2013, ESEC/FSE 2013.

[16]  Jon Andreu,et al.  Design methodology for multifunction vehicle bus devices , 2006 .

[17]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[18]  Luciano Lavagno,et al.  Metropolis: An Integrated Electronic System Design Environment , 2003, Computer.

[19]  Lui Sha,et al.  Data-Centered Runtime Verification of Wireless Medical Cyber-Physical System , 2017, IEEE Transactions on Industrial Informatics.

[20]  Lui Sha,et al.  Safety-Assured Formal Model-Driven Design of the Multifunction Vehicle Bus Controller , 2016, FM.

[21]  Paul Petersen,et al.  Intel®Parallel Inspector , 2011, Encyclopedia of Parallel Computing.

[22]  Rong Zheng,et al.  Guaranteeing Proper-Temporal-Embedding safety rules in wireless CPS: A hybrid formal modeling approach , 2013, 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

[23]  Wang Yi,et al.  Code Synthesis for Timed Automata , 2003 .

[24]  Wang Yi,et al.  TIMES - A Tool for Modelling and Implementation of Embedded Systems , 2002, TACAS.

[25]  Fei He,et al.  Deadlock detection in FPGA design: A practical approach , 2015 .

[26]  Kim G. Larsen,et al.  A Tutorial on Uppaal , 2004, SFM.

[27]  Hee-Jung Byun,et al.  Design and implementation of embedded MVB-ethernet interface , 2011, RACS.

[28]  Frank L. Lewis,et al.  Distributed Fault-Tolerant Control of Virtually and Physically Interconnected Systems With Application to High-Speed Trains Under Traction/Braking Failures , 2016, IEEE Transactions on Intelligent Transportation Systems.

[29]  Zhongqi Li,et al.  Design of Multifunction Vehicle Bus Controller , 2010, CCTA.

[30]  Yu Jiang,et al.  Design of Mixed Synchronous/Asynchronous Systems with Multiple Clocks , 2015, IEEE Transactions on Parallel and Distributed Systems.

[31]  John M. Rushby,et al.  An operational semantics for Stateflow , 2004, International Journal on Software Tools for Technology Transfer.

[32]  Nancy G. Leveson,et al.  Safety Analysis Using Petri Nets , 1987, IEEE Transactions on Software Engineering.

[33]  Yu Jiang,et al.  Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques , 2015, IEEE Transactions on Industrial Electronics.

[34]  Yu Jiang,et al.  Verification and Implementation of the Protocol Standard in Train Control System , 2013, 2013 IEEE 37th Annual Computer Software and Applications Conference.

[35]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[36]  Dawson R. Engler,et al.  A few billion lines of code later , 2010, Commun. ACM.