Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer

An approach for accurately modeling the RC-interconnect delay and gate-loading effects in a hierarchical timing analyzer is presented. The change in gate-loading due to interconnect resistance is considered by an "effective capacitance" approximation. The RC-interconnect path delays are precharacterized in terms of an interpolating polynomial function.

[1]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Lawrence T. Pileggi,et al.  Evaluating RC-interconnect using moment-matching approximations , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  Christopher J. Terman Simulation tools for digital LSI design , 1983 .

[4]  Rathin Putatunda Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips , 1982, DAC 1982.

[5]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  P. R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, ICCAD 1989.

[7]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[8]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.