A New Parallel CODEC Technique for CDMA NoCs

Code division multiple access (CDMA) network-on-chip (NoC) has been proposed for many-core systems due to its data transfer parallelism over communication channels. Consequently, coder–decoder (CODEC) module, which greatly impacts the performance of CDMA NoCs, attracted growing attention in recent years. In this paper, we propose a new parallel CODEC technique for CDMA NoCs. In general, by using a few simple logic circuits with small penalties in area and power, our new parallel (NPC) CODEC can execute the encoding/decoding process in parallel and thus reduce the data transfer latency. To reveal the benefits of our method for on-chip communication, we apply our NPC to CDMA NoCs and perform extensive experiments. From the results, we can find that our method outperforms existing parallel CODECs, such as Walsh-based parallel CODEC (WPC) and overloaded parallel CODEC (OPC). Specifically, it improves the critical point of communication latency (7.3% over WPC and 13.5% over OPC), reduces packet latency jitter by about 17.3% (against WPC) and 71.6% (against OPC), and improves energy efficiency by up to 41.2% (against WPC) and 59.2% (against OPC).

[1]  John A. Silvester,et al.  Spreading code protocols for distributed spread-spectrum packet radio networks , 1988, IEEE Trans. Commun..

[2]  Ahmed A. El Badry,et al.  A CDMA Based Scalable Hierarchical Architecture for Network- On-Chip , 2012 .

[3]  Hafizur Rahaman,et al.  Design of an NoC with on-chip photonic interconnects using adaptive CDMA links , 2012, 2012 IEEE International SOC Conference.

[4]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[5]  Rabah Attia,et al.  BER and SNR analysis of optical network-on-chip using WCDMA codes , 2014, 2014 15th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA).

[6]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[7]  Khaled E. Ahmed,et al.  Aggregated CDMA crossbar for Network-on-Chip , 2016, 2016 28th International Conference on Microelectronics (ICM).

[8]  Andres Kwasinski,et al.  CDMA Enabled Wireless Network-on-Chip , 2014, JETC.

[9]  David Z. Pan,et al.  A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[10]  Mile K. Stojcev,et al.  CDMA bus-based on-chip interconnect infrastructure , 2009, Microelectron. Reliab..

[11]  Mohamed A. Abd El-Ghany,et al.  CDMA technique for Network-on-Chip , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[12]  Daewook Kim,et al.  CDMA-based network-on-chip architecture , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[13]  T. Satya Savithri,et al.  A modified CDMA scheme based NOC architecture for complex SOC applications , 2013, 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

[14]  Xin Wang,et al.  Applying CDMA Technique to Network-on-Chip , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Jason M. Allred,et al.  Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Gerard J. M. Smit,et al.  An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[17]  Songwei Pei,et al.  A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands , 2016, TODE.

[18]  Zhonghai Lu,et al.  A New CDMA Encoding/Decoding Method for on-Chip Communication Network , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Luca P. Carloni,et al.  Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Mohammed M. Farag,et al.  Overloaded CDMA Crossbar for Network-On-Chip , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Gerald E. Sobelman,et al.  Mesh-star Hybrid NoC architecture with CDMA switch , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[22]  Teng Ma,et al.  A dynamic CDMA network for multicore systems , 2014, Microelectron. J..

[23]  Hafizur Rahaman,et al.  Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip , 2016, TECS.

[24]  Mohamed A. Abd El-Ghany,et al.  Hybrid Mesh-Ring wireless Network on Chip for multi-core system , 2012, 2012 International SoC Design Conference (ISOCC).

[25]  Axel Jantsch,et al.  TDM Virtual-Circuit Configuration for Network-on-Chip , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.