Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test

Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16 percent. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.

[1]  Edmund M. Clarke,et al.  Model Checking , 1999, Handbook of Automated Reasoning.

[2]  Armin Biere,et al.  Compressing BMC Encodings with QBF , 2007, BMC@FLoC.

[3]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[4]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[5]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[6]  Rolf Drechsler,et al.  Post-verification debugging of hierarchical designs , 2005, ICCAD 2005.

[7]  Carsten Sinz,et al.  DPvis - A Tool to Visualize the Structure of SAT Instances , 2005, SAT.

[8]  Rolf Drechsler.  Formal Verification of Circuits , 2000, Springer US.

[9]  Marco Benedetti,et al.  sKizzo: A Suite to Evaluate and Certify QBFs , 2005, CADE.

[10]  Armin Biere,et al.  Resolve and Expand , 2004, SAT.

[11]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Andreas G. Veneris.  Fault diagnosis and logic debugging using Boolean satisfiability , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.

[13]  Marco Benedetti,et al.  A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test , 2007, ICCAD 2007.

[14]  Sharad Malik,et al.  Conflict driven learning in a quantified Boolean satisfiability solver , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[15]  Aarti Gupta,et al.  SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems) , 2007 .

[16]  Tracy Larrabee,et al.  Explorations of sequential ATPG using Boolean satisfiability , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[17]  Aarti Gupta,et al.  SAT-Based Scalable Formal Verification Solutions , 2007, Series on Integrated Circuits and Systems.

[18]  Carl Sechen,et al.  VLSI Placement and Global Routing Using Simulated Annealing , 1988 .

[19]  Robert K. Brayton,et al.  Retiming and Resynthesis: A Complexity Perspective , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[21]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[22]  Jason Baumgartner,et al.  Scalable Sequential Equivalence Checking across Arbitrary Design Transformations , 2006, 2006 International Conference on Computer Design.

[23]  Armin Biere,et al.  Bounded model checking , 2003, Adv. Comput..

[24]  A. Prasad Sistla,et al.  The complexity of propositional linear temporal logics , 1982, STOC '82.

[25]  Robert P. Kurshan,et al.  An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment , 2005, CHARME.

[26]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[27]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[28]  Fahiem Bacchus,et al.  Using SAT in QBF , 2005, CP.

[29]  Arlindo L. Oliveira,et al.  On The Complexity Of Power Estimation Problems , 2007 .

[30]  Alan Mishchenko,et al.  Scalable and scalably-verifiable sequential synthesis , 2008, ICCAD 2008.

[31]  Nachum Dershowitz,et al.  Bounded Model Checking with QBF , 2005, SAT.

[32]  J. P. Marques,et al.  GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .