On multiplexed signal tracing for post-silicon debug

Trace-based debug solutions facilitate to eliminate design errors escaped from pre-silicon verification and have gained wide acceptance in the industry. Existing techniques typically trace the same set of signals throughout each debug run, which is not quite effective for catching design errors. In this work, we propose a multiplexed signal tracing strategy that is able to significantly increase debuggability of the circuit. That is, we divide the tracing procedure in each debug run into a few periods and trace different sets of signals in each period. A novel trace signal grouping algorithm is presented to maximize the probability of catching the propagated evidences from design errors, considering the trace interconnection fabric design constraints. Experimental results on benchmark circuits demonstrate the effectiveness of proposed solution.

[1]  Nur A. Touba,et al.  Automated Selection of Signals to Observe for Efficient Silicon Debug , 2009, 2009 27th IEEE VLSI Test Symposium.

[2]  Qiang Xu,et al.  Interconnection fabric design for tracing signals in post-silicon validation , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[3]  Miron Abramovici,et al.  In-System Silicon Validation and Debug , 2008, IEEE Design & Test of Computers.

[4]  Subhasish Mitra,et al.  IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Sandeep Kumar Goel,et al.  Design for debug: catching design errors in digital chips , 2002, IEEE Design & Test of Computers.

[6]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Zeljko Zilic,et al.  Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[8]  Igor L. Markov,et al.  Fixing Design Errors with Counterexamples and Resynthesis , 2007, 2007 Asia and South Pacific Design Automation Conference.

[9]  Sunil Jain,et al.  Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.

[10]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Klaus D. McDonald-Maier,et al.  Debug support for complex systems on-chip: a review , 2006 .

[12]  Michael S. Hsiao,et al.  Multiplexed trace signal selection using non-trivial implication-based correlation , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[13]  Bart Vermeulen,et al.  Silicon debug: scan chains alone are not enough , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[14]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.

[15]  F. Ferrari,et al.  System-on-a-chip verification~methodology and techniques , 2002, IEEE Circuits and Devices Magazine.

[16]  Igor L. Markov,et al.  Simulation-based bug trace minimization with BMC-based refinement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[17]  Don Douglas Josephson,et al.  Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).