Fault clustering technique for 3D memory BISR

Three Dimensional (3D) memory has gained a great momentum because of its large storage capacity, bandwidth and etc. A critical challenge for 3D memory is the significant yield loss due to the disruptive integration process: any memory die that cannot be successfully repaired leads to the failure of the whole stack. The repair ratio of each die must be as high as possible to guarantee the overall yield. Existing memory repair methods, however, follow the traditional way of using redundancies: a redundant row/column replaces a row/column containing few or even one faulty cell. We propose a novel technique specifically in 3D memory that can overcome this limitation. It can cluster faulty cells across layers to the same row/column in the same memory array so that each redundant row/column can repair more “faults”. Moreover, it can be applied to the existing repair algorithms. We design the BIST and BISR modules to implement the proposed repair technique. Experimental results show more than 71% enhancement of the repair ratio over the global 3D GESP solution and 80% redundancy-cost reduction, respectively.

[1]  Gabriel H. Loh,et al.  3D-Integrated SRAM Components for High-Performance Microprocessors , 2009, IEEE Transactions on Computers.

[2]  Sungho Kang,et al.  A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories , 2015, IEEE Transactions on Reliability.

[3]  Kunle Olukotun,et al.  Energy-Efficient Abundant-Data Computing: The N3XT 1,000x , 2015, Computer.

[4]  Sungho Kang,et al.  An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Yu-Jen Huang,et al.  Yield-enhancement techniques for 3D random access memories , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[6]  Ding-Ming Kwai,et al.  3D-IC BISR for stacked memories using cross-die spares , 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

[7]  Dae-Hyun Kim,et al.  ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates , 2013, ISCA.

[8]  K. Soejima,et al.  A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.

[9]  Qiang Xu,et al.  Yield enhancement for 3D-stacked memory by redundancy sharing across dies , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[11]  Masahide Matsumoto,et al.  A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology , 2014, IEEE Journal of Solid-State Circuits.

[12]  Sukhan Lee,et al.  CiDRA: A cache-inspired DRAM resilience architecture , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[13]  Ding-Ming Kwai,et al.  Memory Repair by Die Stacking with through Silicon Vias , 2009, 2009 IEEE International Workshop on Memory Technology, Design, and Testing.

[14]  Hsien-Hsin S. Lee,et al.  Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[15]  Meng-Fan Chang,et al.  Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM) , 2011, 2011 9th IEEE International Conference on ASIC.

[16]  Yong-Bin Kim,et al.  Balanced redundancy utilization in embedded memory cores for dependable systems , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[17]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[18]  Swapnil Bahl A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[19]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.