Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation

Single electron transistor (SET) has been envisaged as a potential device to achieve high-end performance in deep sub-micron technologies. The paper innovatively presents a 4-bit ALU based on single electron transistor (SET). The proposed logic design model is encouragingly operational at room temperature. SET based ALU has been designed, simulated and optimized with incorporation of all the parameters in the feasible fabrication range. Design and optimization have been performed in hierarchical manner i.e. from basic cells (device or transistor level) to circuit level. Performance comparison between SET, MOS and hybrid SET-MOS based circuits has been evaluated. From the simulation results, it is investigated that ALU based on SET with optimized parameters is more efficient compared to its MOS counterpart. The percentage improvements in SET over CMOS based ALU design in power, delay and power-delay product are 65.4%, 79.7% and 92.9% respectively. These improvements in SET over hybrid SET-MOS based ALU are 0.6%, 33.7% and 33.8 % respectively. The analyses have been performed at 45nm technology node using Cadence EDA tool.

[1]  Subir Kumar Sarkar,et al.  Hybrid single electron transistor based low power consuming 4-bit parallel adder/subtractor circuit in 65 nanometer technology , 2014, 2014 17th International Conference on Computer and Information Technology (ICCIT).

[2]  Dominique Drouin,et al.  Single-electron transistors with wide operating temperature range , 2007 .

[3]  Huaxiang Lu,et al.  Simulation of Single Electronic Device and Robust Circuit Construction , 2007, 2007 IEEE International Conference on Control and Automation.

[4]  S. Mahapatra,et al.  Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design , 2004, IEEE Transactions on Electron Devices.

[5]  Sumit R. Vaidya,et al.  DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN , 2010 .

[6]  Ashok K. Goel,et al.  Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature , 2008, Microelectron. J..

[7]  D. Drouin,et al.  Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation , 2012, IEEE Transactions on Electron Devices.

[8]  Subir Kumar Sarkar,et al.  Design and performance analysis of reversible logic based ALU using hybrid single electron transistor , 2014, 2014 Recent Advances in Engineering and Computational Sciences (RAECS).

[9]  Dominique Drouin,et al.  Room temperature double gate Single Electron Transistor based standard cell library , 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[10]  D. Samanta,et al.  A simple SET-MOS universal hybrid circuit for realization of all basic logic functions , 2012, IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012).

[11]  A.M. Ionescu,et al.  A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[12]  Adrian M. Ionescu,et al.  Hybrid CMOS Single-Electron-Transistor Device And Circuit Design , 2006 .

[13]  Z. Durrani.  Single-Electron Devices and Circuits in Silicon , 2009 .

[14]  P. K. Dakhole,et al.  Design and implementation of single electron transistor N-BIT multiplier , 2014, 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014].

[15]  Chao Zhang,et al.  Macromodeling of realistic single electron transistors for large scale circuit simulation , 2010, 2010 3rd International Nanoelectronics Conference (INEC).

[16]  P. K. Dakhole,et al.  Design and implementation of four bit arithmetic and logic unit using hybrid single electron transistor and MOSFET at 120nm technology , 2015, 2015 International Conference on Pervasive Computing (ICPC).

[17]  Rutu Parekh,et al.  SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit , 2014, Microelectron. J..

[18]  M. Dousti,et al.  An improved macro-model for simulation of single electron transistor (SET) using HSPICE , 2009, 2009 IEEE Toronto International Conference Science and Technology for Humanity (TIC-STH).

[19]  D. Drouin,et al.  A Nanodamascene Process for Advanced Single-Electron Transistor Fabrication , 2008, IEEE Transactions on Nanotechnology.