Super recursive baselines: a family of new interconnection networks with high performance/cost ratios
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[1] Janak H. Patel. Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.
[2] Daniel M. Dias,et al. Analysis and Simulation of Buffered Delta Networks , 1981, IEEE Transactions on Computers.
[3] Tse-Yun Feng,et al. On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.
[4] Duncan H. Lawrie,et al. Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.
[5] Thomas G. Robertazzi. Performance of ProcessorMemory Interconnections for Multiprocessors , 1993 .