Method and device for caching and transmitting of Ethernet data frames in FPGA (field programmable gate array)

The invention discloses a method and a device for caching and transmitting of Ethernet data frames in FPGA (field programmable gate array). The method includes according to the minimum Ethernet data frame package length, deeply dividing a data frame caching and storing unit and the like into a plurality of small-particle data frame storing units; writing the Ethernet data frame into the data frame caching and storing unit, particularly storing identifiers of Ethernet data frame in a 0*0 address of an initial small-particle data frame storing unit RAM (random access memory) (n), storing sequence numbers and addresses of an initial small-particle data frame storing unit RAM (n+m) where a last byte of the Ethernet data frame existing in a 0 *1 address and a 0*2 address, and sequentially storing data frame net load byte from a 0*3 address; sequentially reading the cached data frame net load byte from the 0*3 address of the current initial small-particle data frame storing unit RAM (n) to the last byte address of the small-particle data frame storing unit RAM (n+m), and adding 1 to the sequence number n+m to read the next data frame. By the use of the method and the device, caching and transmitting of the Ethernet data frame is achieved, use ratio of RAM in the FPGA, and stability of the whole structure during the caching and transmitting is guaranteed.