A novel genetic algorithm for the automated design of performance driven digital circuits

Presents a genetic algorithm for the design of high-performance arithmetic circuits for evolvable hardware applications. A distinct feature of the algorithm is its ability to directly evolve and evaluate circuits in a hardware description language (HDL), within a novel environment termed the Virtual Chip. Because the Virtual Chip evolves circuit structures within a HDL, detailed simulation and analysis of each circuit is possible with any technology-specific component library. This feature allows accurate analysis of performance issues such as timing and area. The paper describes the genetic algorithm and the hardware evaluation environment, and provides results with a number of benchmark arithmetic circuits evolved under different performance-driven timing and area constraints. Our results reveal that the genetic algorithm is able to exploit the flexibility provided by a novel chromosome architecture, and utilise a combination of primitive gates and macro components from a component library in order to produce circuits which operate well within timing restrictions. The validity of our results are further supported by comparing the performance of functionally equivalent circuits generated using standard high-level design methodologies.