Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance
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[1] Shunsuke Miyamoto,et al. Clock event suppression algorithm of VELVET and its application to S-820 development , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[2] Masayuki Miyoshi,et al. An Extensive Logic Simulation Method of Very Large Scale Computer Design , 1986, 23rd ACM/IEEE Design Automation Conference.
[3] Tokinori Kozawa,et al. Principles of design automatioon system for very large scale computer design , 1986, DAC 1986.
[4] Tokinori Kozawa,et al. Principles of Design Automation System for Very Large Scale Computer Design , 1986, 23rd ACM/IEEE Design Automation Conference.
[5] Yooji Tsuchiya,et al. Establishment of Higher Level Logic Design for Very Large Scale Computer , 1986, DAC 1986.
[6] Ernst G. Ulrich. A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression , 1983, 20th Design Automation Conference Proceedings.
[7] Katsuya Sato,et al. Logic Verification System for Very Large Computers Using LSI's , 1979, 16th Design Automation Conference.
[8] Masayuki Miyoshi,et al. An Extensive Logic Simulation Method of Very Large Scale Computer Design , 1986, DAC 1986.