A frequency synthesizer with low-power and very short settling time is introduced, which utilizes two-point channel control paths. While the main-path is the same as normal channel controls, a digital-to-analog converter (DAC) with tunable gain is used for the compensation-path to form a feed-forward direct voltage-controlled oscillator (VCO) control path. When the two paths are ideally matched, the two-point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor-loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near-zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase-locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is − 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.
(A frequency synthesizer with two-point channel control composed of main-and compensation-paths is introduced for fast settling time performance. Any mismatch between the two paths is effectively tuned out by controlling the combined gain of a linearized VCO and a resistor loaded tunable DAC. Even for a narrow 20 kHz PLL bandwidth, the synthesizer achieved near zero settling time at 2.4 GHz, with phase noise of −116.6 dBc/Hz at 1 MHz offset and total power consumption of 4.2 mW.)
[1]
V. Cheung,et al.
A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process
,
2003,
IEEE J. Solid State Circuits.
[2]
Kwyro Lee,et al.
Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process
,
2006,
IEEE Transactions on Microwave Theory and Techniques.
[3]
S. Pellerano,et al.
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider
,
2004,
IEEE Journal of Solid-State Circuits.
[4]
Kiat Seng Yeo,et al.
GHz programmable counter with low power consumption
,
2003
.
[5]
B. Neurauter,et al.
GSM 900/DCS 1800 fractional-N modulator with two-point-modulation
,
2002,
2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).
[6]
SeongHwan Cho,et al.
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications
,
2004,
IEEE Journal of Solid-State Circuits.
[7]
Juha Kostamovaara,et al.
Speeding up an integer-N PLL by controlling the loop filter charge
,
2003
.
[8]
Poras T. Balsara,et al.
All-Digital PLL With Ultra Fast Settling
,
2007,
IEEE Transactions on Circuits and Systems II: Express Briefs.
[9]
Jaeha Kim,et al.
Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach
,
2003,
IEEE Trans. Circuits Syst. II Express Briefs.