An Efficient FFT Engine With Reduced Addressing Logic

In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 N-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 mum technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.

[1]  M. Swamy,et al.  A new radix-2/8 FFT algorithm for length-q/spl times/2/sup m/ DFTs , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Han Yue-qiu.  A Fast Address Generation Scheme for FFT Processor , 2006 .

[3]  D. Cohen.  Simplified control of FFT hardware , 1976 .

[4]  Liang Yang,et al.  An efficient locally pipelined FFT processor , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Richard M. Jiang,et al.  An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting , 2007, IEEE Transactions on Consumer Electronics.

[6]  J. Saniie,et al.  Efficient FFT engine with reduced addressing logic , 2007, 2007 IEEE International Conference on Electro/Information Technology.

[7]  Yu Tai Ma,et al.  A VLSI-oriented parallel FFT algorithm , 1996, IEEE Trans. Signal Process..

[8]  Lewis Johnson,et al.  Conflict free memory addressing for dedicated FFT hardware , 1992 .

[9]  Xiaojin Li,et al.  A Low Power and Small Area FFT Processor for OFDM Demodulator , 2007, IEEE Transactions on Consumer Electronics.

[10]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[11]  M. Omair Ahmad,et al.  A new radix-2/8 FFT algorithm for length-q×2m DFTs , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[12]  T. M. Hopkinson,et al.  A pipelined, high-precision FFT architecture , 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

[13]  Yutai Ma,et al.  An effective memory addressing scheme for FFT processors , 1999, IEEE Trans. Signal Process..

[14]  Lars Wanhammar,et al.  A hardware efficient control of memory addressing for high-performance FFT processors , 2000, IEEE Trans. Signal Process..

[15]  Y. Wang,et al.  Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors , 2007, IEEE Transactions on Signal Processing.

[16]  Weidong Li,et al.  A pipeline FFT processor , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).