Hierarchical model order reduction for signal-integrity interconnect synthesis

The goal of this paper is to establish the basic framework and theoretical foundations for the hierarchical model order reduction with an emphasis on signal integrity analysis. The proposed algorithm, HMOR (Hierarchical Model Order Reduction), performs model reduction for both linear elements and independent sources simultaneously and hierarchically. Hence it is very suitable for fast timing and signal integrity analysis ~br tightly coupled RLC interconnects or with lots of independent sources such as power delivery circuits. It can fully utilize RICE [9] and PRIMA [11] to perform moment matching in the subcircuits to achieve the best performance and reduction ratio with passivity guarantee. HMOR significantly speeds up the sinmlation time tbr minor modified circuits. Combining with hierarchical interconnect synthesis algorithms such as routing, sizing and repeater insertion, HMOR can speed up N times over flat analysis where N is t'he number of circuit elements in the tree. In addition, we also develop a FM-based partition algorithm to partition tile circuit into small weak-coupled blocks to enhance runtime. This extension enables HMOR to handle the interconnect topology with loops, meshes, even with complicated current return paths.

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