On design and performance of VLSI based parallel multiplier

This paper introduces the VLSI design and layout of a (log2n) time n-bit binary parallel multiplier for two unsigned operands. Proposed design consists of partitioning the multiplier and multiplicand bits Into four groups of n/4 bits each and then reducing the matrix of sixteen product terms using three to two parallel counters and Brent-Kung (log n) time parallel adder. Area-time performance of the present scheme has been compared with the existing schemes for parallel multipliers. Regular and recursive design of the multiplier is shown to be suitable for VLSI implementation and an improved table look up multiplier has been used to form the basis of the recursive design scheme.