Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption in 1R crossbars, is used as a large-scale memory system. In this paper, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers defined faults caused by electrical defects. The test time of the proposed test algorithm is reduced significantly compared with previous test algorithms that are enhanced for CMOL architecture.

[1]  M. Prezioso,et al.  A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit , 2017, Scientific reports.

[2]  Eby G. Friedman,et al.  VTEAM – A General Model for Voltage Controlled Memristors , 2014 .

[3]  Sachhidh Kannan,et al.  Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories , 2013, IEEE Transactions on Nanotechnology.

[4]  Weizheng Wang,et al.  Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar , 2017 .

[5]  Weizheng Wang,et al.  Efficient March test algorithm for 1T1R cross-bar with complete fault coverage , 2016 .

[6]  Jin-Fu Li,et al.  Fault modeling and testing of 1T1R memristor memories , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

[7]  Frederick T. Chen,et al.  RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme , 2015, IEEE Transactions on Computers.

[8]  Naifeng Jing,et al.  Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  Cheng-Wen Wu,et al.  RAMSES: a fast memory fault simulator , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[10]  Peng Liu,et al.  Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm , 2015, IEICE Electron. Express.

[11]  Said Hamdioui,et al.  Testing Open Defects in Memristor-Based Memories , 2015, IEEE Transactions on Computers.

[12]  K.K. Likharev,et al.  Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing , 2007, IEEE Transactions on Nanotechnology.