On the effect of stuck-at faults on delay-insensitive nanoscale circuits

Nanocomputing system design has been attracting attention in recent years. Regular structure and reliable timing control are the two requirements to implement nanoscale circuits. A cellular array has highly regular structure. The cells are adjacent to each other and are able to process signals based on simple transition rules. In delay-insensitive circuits the delay on a signal path does not affect circuit behavior. The combination of delay-insensitive circuits and cellular arrays make it feasible to implement silicon-based nanoscale circuits. However, little work has been done on the test of such circuits. This paper provides a complete analysis of the effect of stuck-at faults in delay-insensitive circuits on cellular arrays.