CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms

Heterogeneous computing brings the opportunity to catch up with the increasing demands of modern computing tasks. For this purpose, the CPU-FPGA platform is promising due to the high flexibility of FPGA, which enables customization for various computing tasks to boost performance and energy efficiency. Nowadays, shared coherent cache based CPU-FPGA systems (like Intel HARP and IBM POWER8 with CAPI) are proposed to enhance the communication efficiency between CPU and FPGA and simplify the programming model. In such systems, a coherent cache is attached to FPGA for the quick memory access from FPGA, and its behavior dominates the performance of the FPGA and the entire system. However, the FPGA execution tends to encounter severe cache misses on the FPGA cache, which degrades the FPGA acceleration benefits. To solve this problem, we propose CAMAS, a static and dynamic coordinated cache management approach to reduce the FPGA cache misses and enhance the AFU performance. In the static step, reuse distance analysis is applied to the memory access trace from FPGA to characterize the accessed cachelines into three types according to their locality level. Then a dynamic control with a learning mechanism performs bypassing or caching for the returned cachelines at the cache miss according to the corresponding type. Our approach combines compile-time analysis to determine the caching or bypassing preference with the run-time management equipped with a dynamic learning mechanism. Experiments on Polybench applications demonstrate an average performance improvement of 24.92% using CAMAS.