M/sup 2/R: multilayer routing algorithm for high-performance MCMs

We introduce a new multilayer routing strategy for high-performance MCMs whose objective is to route all nets optimizing routing performance and to satisfy various design constraints (e.g., minimizing coupling between vias as well as between signal lines and minimizing discontinuities such as vias and bends). First we introduce the Pin Pre-wiring and Redistribution Problem, which redistributes the pins or prewired subnets uniformly over the MCM substrate using pin redistribution layers. Pin redistribution is very important in MCM design. Our experience shows that it not only provides a global distribution for the pins congested in the chip site over the chip layer so as to ease the future routing difficulty, but also reduces the capacitive coupling between vias induced by many layers (up to 63 layers) by separating the pins far apart. The goal of the problem is to minimize the number of layers required to redistribute the entire set. An effective approach is proposed for solving this problem. Next we develop four effective algorithms for signal distribution, i.e., two variations on both single-layer routing and xy plane-pair routing paradigms. Based on these algorithms, a mixed version of single-layer routing and xy plane-pair routing techniques is proposed to establish a good trade-off between them to favor circuit performance and/or design objective instead of overemphasizing on the area minimization. One strategy is to apply single-layer routing iteratively until /spl alpha/ % of the nets are routed, then route the remaining (100/spl minus//spl alpha/)% nets by xy plane-pair routing process. This provides the designer with a trade-off (e.g., between the number of layers and total number of vias) and shows the versatility of the proposed techniques. Various strategies are compared using practical MCM examples (each MCM has 25-100 ICs, 25-60 I/Os per IC, and 50-1,200 nets). >

[1]  Malgorzata Marek-Sadowska An Unconstrained Topological Via Minimization Problem for Two-Layer Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[3]  Wayne Wei-Ming Dai,et al.  Topological routing in SURF: generating a rubber-band sketch , 1991, 28th ACM/IEEE Design Automation Conference.

[4]  Chak-Kuen Wong,et al.  Layer assignment for multichip modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  A. Reisman,et al.  A thermal module design for advanced packaging , 1987 .

[6]  Wentai Liu,et al.  Unconstrained via minimization for topological multilayer routing , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sung-Mo Kang,et al.  Detailed layer assignment for MCM routing , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Chak-Kuen Wong,et al.  Single-layer global routing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  John U. Knickerbocker,et al.  IBM System/390 air-cooled alumina thermal conduction module , 1991, IBM J. Res. Dev..

[10]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Massoud Pedram,et al.  Automatic Layout of Silicon-On-Silicon Hybrid Packages , 1989, 26th ACM/IEEE Design Automation Conference.

[12]  Sung-Mo Kang,et al.  Crosstalk-minimum layer assignment , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[13]  Jason Cong,et al.  A fast multilayer general area router for MCM designs , 1992, EURO-DAC '92.

[14]  Majid Sarrafzadeh,et al.  Single-layer global routing , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[15]  H. H. Chen,et al.  Wiring And Crosstalk Avoidance In Multi-chip Module Design , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.