Cross-layer custom instruction selection to address PVTA variations and soft error

Abstract •Process, Voltage, Temperature, and Aging (PVTA) variations introduce remarkable timing unpredictability to Custom Instructions (CIs) manufactured at nanoscale technology node. Moreover, shrinking the feature size to nanometer scales makes soft error another critical issue of CIs. To address these concerns, we propose a cross-layer CI selection methodology as a helping rein in the reliability decrease due to the combined effects of PVTA variations and soft error. According to this approach, in a top-down fashion, the information obtained at application and architecture levels is projected into device and circuit levels in order to accurately assess Soft Error Rate (SER) and the effects of the PVTA variations on the lifetimes and delays of CIs. Next, based on a bottom-up approach, timing information and SER of the underlying hardwares are captured at application-level CI selection merit functions. Experiments illustrate that our proposed cross-layer reliability-aware CI selection techniques extend the lifetime of the system up to 6.2 ×, while, SER is decreased by 2.5 × on average.

[1]  Quan Chen,et al.  A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[3]  David Blaauw,et al.  Statistical Timing Analysis: From Basic Principles to State of the Art , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Sujit Dey,et al.  A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  James F. Ziegler,et al.  Terrestrial cosmic rays , 1996, IBM J. Res. Dev..

[6]  Mehdi Baradaran Tahoori,et al.  Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic , 2012, 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[7]  Narayanan Vijaykrishnan,et al.  Variation Impact on SER of Combinational Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[8]  J. Torrellas,et al.  VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.

[9]  Mark Mohammad Tehranipoor,et al.  Efficient selection and analysis of critical-reliability paths and gates , 2012, GLSVLSI '12.

[10]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[11]  Elizabeth M. Rudnick,et al.  A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.

[12]  David Blaauw,et al.  Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[13]  Kueing-Long Chen,et al.  The case of AC stress in the hot-carrier effect , 1986, IEEE Transactions on Electron Devices.

[14]  Josep Torrellas,et al.  Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[15]  M. Anis,et al.  Power Yield Analysis Under Process and Temperature Variations , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Sani R. Nassif,et al.  Analyzing the impact of process variations on parametric measurements: Novel models and applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[17]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[18]  Günhan Dündar,et al.  An integer linear programming approach for identifying instruction-set extensions , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[19]  Sied Mehdi Fakhraie,et al.  CIVA: Custom instruction vulnerability analysis framework , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[20]  Luca Benini,et al.  Hierarchically Focused Guardbanding: An adaptive approach to mitigate PVT variations and aging , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Scott A. Mahlke,et al.  Automated custom instruction generation for domain-specific processor acceleration , 2005, IEEE Transactions on Computers.

[22]  Bo Yang,et al.  Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[23]  Alan Wood,et al.  The impact of new technology on soft error rates , 2011, 2011 International Reliability Physics Symposium.

[24]  Deming Chen,et al.  Temperature aware statistical static timing analysis , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[25]  Roberto da Silva,et al.  Logarithmic behavior of the degradation dynamics of metal?oxide?semiconductor devices , 2010, 1002.3571.

[26]  Sied Mehdi Fakhraie,et al.  Reliability-aware cross-layer custom instruction screening , 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[27]  Mircea R. Stan,et al.  Modeling and analyzing NBTI in the presence of Process Variation , 2011, 2011 12th International Symposium on Quality Electronic Design.

[28]  Tulika Mitra,et al.  Scalable custom instructions identification for instruction-set extensible processors , 2004, CASES '04.

[29]  Diana Marculescu,et al.  A systematic approach to modeling and analysis of transient faults in logic circuits , 2009, 2009 10th International Symposium on Quality Electronic Design.

[30]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[31]  Diana Marculescu,et al.  MARS-C: modeling and reduction of soft errors in combinational circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[32]  Donald J. Patterson,et al.  Computer organization and design: the hardware-software interface (appendix a , 1993 .

[33]  Narayanan Vijaykrishnan,et al.  SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[34]  Paolo Bonzini,et al.  Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Paolo Ienne,et al.  Exact and approximate algorithms for the extension of embedded processor instruction sets , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  Mehdi Baradaran Tahoori,et al.  Instruction-set extension under process variation and aging effects , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[37]  Giuseppe La Rosa,et al.  A review of hot-carrier degradation mechanisms in MOSFETs , 1996 .

[38]  G. Groeseneken,et al.  Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.

[39]  S. Deora,et al.  A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery , 2011, 2011 International Reliability Physics Symposium.

[40]  Meeta Sharma Gupta,et al.  Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[41]  Mehdi Kamal,et al.  Timing variation-aware custom instruction extension technique , 2011, 2011 Design, Automation & Test in Europe.

[42]  B. Kaczer,et al.  Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping , 2011, IEEE Transactions on Electron Devices.

[43]  Mehdi Kamal,et al.  Considering the effect of process variations during the ISA extension design flow , 2013, Microprocess. Microsystems.

[44]  Bin Zhang,et al.  FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[45]  Yu Cao,et al.  Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[46]  Ogawa,et al.  Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.

[47]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[48]  Mehdi Baradaran Tahoori,et al.  An analytical approach for soft error rate estimation in digital circuits , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[49]  Mark Mohammad Tehranipoor,et al.  Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluation , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[50]  Sied Mehdi Fakhraie,et al.  Vulnerability Analysis for Custom Instructions , 2012, 2012 15th Euromicro Conference on Digital System Design.

[51]  Mehdi Baradaran Tahoori,et al.  Chip-level modeling and analysis of electrical masking of soft errors , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[52]  Mehdi Kamal,et al.  Capturing and mitigating the NBTI effect during the design flow for extensible processors , 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[53]  Farshad Firouzi,et al.  An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects , 2011, Microelectron. Reliab..

[54]  Bharat L. Bhuva,et al.  Simulation of SEU transients in CMOS ICs , 1991 .

[55]  Abhijit Chatterjee,et al.  Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.

[56]  Francky Catthoor,et al.  Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits , 2014, IEEE Transactions on Electron Devices.

[57]  Peter Lidén,et al.  A switch-level algorithm for simulation of transients in combinational logic , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[58]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[59]  E. Mintarno,et al.  Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[60]  Mehdi Baradaran Tahoori,et al.  Statistical analysis of BTI in the presence of process-induced voltage and temperature variations , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[61]  David Blaauw,et al.  Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[62]  N. Seifert,et al.  Chip-level soft error estimation method , 2005, IEEE Transactions on Device and Materials Reliability.

[63]  Hai Zhou,et al.  Fast Estimation of Timing Yield Bounds for Process Variations , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[64]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[65]  Kevin Skadron,et al.  Impact of process variations on multicore performance symmetry , 2007 .

[66]  M. Elmasry,et al.  NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias , 2012, IEEE Transactions on Semiconductor Manufacturing.

[67]  Mehdi Baradaran Tahoori,et al.  Incorporating the impacts of workload-dependent runtime variations into timing analysis , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[68]  Saeed Safari,et al.  A cross-layer SER analysis in the presence of PVTA variations , 2015, Microelectron. Reliab..

[69]  Martin D. F. Wong,et al.  Fast algorithms for IR drop analysis in large power grid , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[70]  Meeta Sharma Gupta,et al.  Tribeca: Design for PVT variations with local recovery and fine-grained adaptation , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[71]  Qin Tang,et al.  Transistor-level gate model based statistical timing analysis considering correlations , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[72]  Saeed Safari,et al.  An instance-based SER analysis in the presence of PVTA variations , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[73]  Mehdi Baradaran Tahoori,et al.  Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[74]  Tilman Wolf,et al.  PacketBench: a tool for workload characterization of network processing , 2003, 2003 IEEE International Conference on Communications (Cat. No.03CH37441).

[75]  Mehdi Kamal,et al.  An architecture-level approach for mitigating the impact of process variations on extensible processors , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[76]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.