An Optimization Method of TLB Architecture

Aiming at the problem of the inefficiency of the Translation Look-aside Buffer(TLB) of a homegrown microprocessor,based on the analysis of current virtual to real address mapping program,a method of TLB architecture optimization is put forward,which is to setup a separate virtual to real address mapping cache of the base address of third level page tables,decreasing the occurrence of replacement of higher level page table entries by lower level ones.After evaluation using SPEC CPU2000 benchmark,the Double Miss(DM) rate of the data TLB of almost half of the benchmarks is dropped down by 60% at least and some of the benchmarks are decreased by 90% above,such optimization can reduce data TLB miss rate effectively.