Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators

Power delivery networks with distributed on-chip voltage regulators (VRs) serve as an effective way for fast localized voltage regulation within modern microprocessors. Without careful consideration of the interactions among the distributed VRs and the power grid, unbalanced current sharing (CS) among those regulators may, however, lead to efficiency degradations, stability, and reliability issues, and even malfunctions of the regulators. This paper is a first attempt to investigate the efficiency, stability, and reliability implications of unbalanced CS among distributed on-chip VRs. Benefits of balanced CS are demonstrated with concrete examples, showing the necessity of an appropriate current balancing scheme. An adaptive reference voltage control method and the corresponding control algorithms specifically for distributed on-chip VRs are proposed to balance the CS among regulators at different locations. The proposed techniques successfully balance the CS among distributed VRs and can be applied to different regulator types. Simulation results based on practical microprocessor setups confirm the efficiency, stability, and reliability implications.

[1]  Eby G. Friedman,et al.  Stability of Distributed Power Delivery Systems With Multiple Parallel On-Chip LDO Regulators , 2016, IEEE transactions on power electronics.

[2]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  Slobodan Cuk,et al.  A general unified approach to modelling switching-converter power stages , 1976, 1970 IEEE Power Electronics Specialists Conference.

[4]  Fabrice Paillet,et al.  FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

[5]  Kevin Skadron,et al.  Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Cheng Huang,et al.  An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency , 2013, IEEE Journal of Solid-State Circuits.

[7]  Kevin Skadron,et al.  Architecture implications of pads as a scarce resource , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[8]  Lieven Eeckhout,et al.  Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[9]  Kevin Skadron,et al.  Walking pads: Managing C4 placement for transient voltage noise minimization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  G. Rincón-Mora,et al.  A comprehensive power analysis and a highly efficient, mode-hopping DC-DC converter , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[11]  Kevin Skadron,et al.  HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects , 2003 .

[12]  Pak Kwong Chan,et al.  A 0.9-/spl mu/A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Christophe Basso,et al.  Switch-Mode Power Supplies Spice Simulations and Practical Designs , 2008 .

[14]  Zhiyu Zeng,et al.  Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation , 2010, Design Automation Conference.

[15]  Jiin-Chuan Wu,et al.  A Monolithic Current-Mode Buck Converter With Advanced Control and Protection Circuits , 2007, IEEE Transactions on Power Electronics.

[16]  Selçuk Köse,et al.  Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[17]  Massoud Pedram,et al.  Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Peng Li,et al.  Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  H. Ryssel,et al.  Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies , 2010 .

[20]  Eby G. Friedman,et al.  Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[22]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[23]  Ting Yu,et al.  Efficient simulation-based optimization of power grid with on-chip voltage regulator , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[24]  Eby G. Friedman,et al.  Distributed On-Chip Power Delivery , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[25]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[26]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[27]  Kevin Skadron,et al.  Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC , 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[28]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[29]  Renatas Jakushokas,et al.  On-Chip Power Delivery and Management , 2016 .

[30]  Jaber A Abu-Qahouq,et al.  Analysis and Design of N-Phase Current-Sharing Autotuning Controller , 2010, IEEE Transactions on Power Electronics.

[31]  Mikko Hankaniemi,et al.  Dynamical Profile of Switched-Mode Converter - Fact or Fiction? , 2007 .

[32]  Bengt Johansson DC-DC Converters - Dynamic Model Design and Experimental Verification , 2005 .

[33]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[34]  Oscar Garcia,et al.  Efficiency improvement in multiphase converter by changing dynamically the number of phases , 2006 .

[35]  Eby G. Friedman,et al.  Effective Resistance of a Two Layer Mesh , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[36]  Seth R. Sanders,et al.  Phase Current Unbalance Estimation in , 2008 .

[37]  Eby G. Friedman,et al.  On-chip point-of-load voltage regulator for distributed power supplies , 2010, GLSVLSI '10.

[38]  Sheldon X.-D. Tan,et al.  Physics-based electromigration assessment for power grid networks , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[39]  Gu-Yeon Wei,et al.  Quantifying sources of error in McPAT and potential impacts on architectural studies , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[40]  Nitin Borkar,et al.  System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[41]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[42]  Fred C. Lee,et al.  Optimizing design for low voltage DC-DC converters , 1997, Proceedings of APEC 97 - Applied Power Electronics Conference.

[43]  Seongwon Kim,et al.  Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage , 2012, IEEE Journal of Solid-State Circuits.

[44]  José G. Delgado-Frias,et al.  VLSI for Neural Networks and Artificial Intelligence , 1994, Springer US.

[45]  Eby G. Friedman,et al.  Efficient algorithms for fast IR drop analysis exploiting locality , 2012, Integr..