Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories
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Wei Zhang | Zhe Wang | Xiaowen Wu | Jiang Xu | Yaoyao Ye | Zhehui Wang | Mahdi Nikdast | Xuan Wang
[1] Avinoam Kolodny,et al. Effective Radii of On-Chip Decoupling Capacitors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Malgorzata Marek-Sadowska,et al. Timing-Aware Power-Noise Reduction in Placement , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] David Howard,et al. Challenges in sleep transistor design and implementation in low-power designs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[4] Yu Wang,et al. On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip , 2013, IEEE Transactions on Parallel and Distributed Systems.
[5] Asim J. Al-Khalili,et al. Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Jan M. Rabaey,et al. SRAM supply voltage scaling: A reliability perspective , 2009, 2009 10th International Symposium on Quality Electronic Design.
[7] Wei Zhang,et al. A NoC Traffic Suite Based on Real Applications , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.
[8] Hsien-Hsin S. Lee,et al. 3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.
[9] Pradip Bose,et al. A case for guarded power gating for multi-core processors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.