A High-Speed RS Decoder Using Extended BM Algorithm Based on FPGA

A high-speed RS(Reed-Solomon) decoder architecture is presented. BM algorithm is irregular and has a longer critical path delay which is dependent on the error-correcting capability of the code. An architecture based on the eE(extended Euclidean) algorithm is used in the majority of the implementations for the sake of the irregular architectures in BM algorithm. An architecture based on a modified BM algorithm is regular and has less critical path delay. Finally, a new GF multiplied architecture is adopted for regular architecture.