An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on–chip current/voltage references

This work proposes an 11b 70MHz CMOS pipelined A/D converter (ADC) as one of core circuit blocks for high-speed VDSL system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage (I/V) references and a merged-capacitor switching (MCS) technique to improve ADC performances. The ADC implemented in a 0.18µm n-well single-poly quad-metal CMOS technology shows the maximum SNDR of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the SFDR of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured DNL and INL of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm2and the ADC consumes 49 mW at 70 MSample/s at a 1.8 V supply.

[1]  P.J. Hurst,et al.  A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  K. Leung,et al.  A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device , 2002, IEEE J. Solid State Circuits.

[3]  Chan-Hong Park,et al.  A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[4]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[5]  F. Tsay,et al.  A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  M. Timko,et al.  A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[7]  A.A. Abidi,et al.  A 10 b, 400 MS/s glitch-free CMOS D/A converter , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[8]  Asad A. Abidi,et al.  A I0-bit, 100 MS/s CMOS A/D Converter , 1996, Proceedings of Custom Integrated Circuits Conference.

[9]  Yong Hoon Lee,et al.  A 300mW programmable QAM transceiver for VDSL applications , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  P.R. Gray,et al.  A precision curvature-compensated CMOS bandgap reference , 1983, IEEE Journal of Solid-State Circuits.

[11]  Seung-Hoon Lee,et al.  A Temperature and Supply-Voltage Insensitive CMOS Current Reference , 1999 .

[12]  Un-Ku Moon,et al.  A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[13]  Kwang Young Kim,et al.  A 10-b, 100-MS/s CMOS A/D converter , 1997 .

[14]  T. R. Viswanathan,et al.  A CMOS bandgap reference without resistors , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).