56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process

This paper presents a 56Gb/s PAM-4 optical receiver analog frontend circuits which consists of three inverter stages TIA with resistive feedback in the first and third stages. An adaptively-tuned continuous-time linear equalizer (CTLE) is cascaded after the TIA for improved sensitivity and bandwidth. The overall gain is controlled by an automatic gain control (AGC) circuits to avoid the large input optical power saturates the TIA, thus distorting the PAM-4 signals. The frontend receiver circuits is designed in an advanced FinFET technology and overall gain achieves 68 dBO with a 22 GHz bandwidth. The simulated input referred current rms noise is 2.86 μA. Total chip power is 6.3 mW from a 0.83 V supply. The chip active area is 150μm × 100 μm.

[1]  Calvin Plett,et al.  A 40 Gb/s transimpedance amplifier in 65 nm CMOS , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[2]  Marco Fiorentino,et al.  A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Pervez M. Aziz,et al.  A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[4]  W. Walker,et al.  A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Paul D. Townsend,et al.  An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOS , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  Xi Chen,et al.  Dynamic voltage and frequency scaling for shared resources in multicore processor designs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Xi Chen,et al.  In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[8]  Cheng Li,et al.  LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip , 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Cheng Li,et al.  A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier , 2013, IEEE Journal of Solid-State Circuits.