Addressing parallel display drive circuit and system thereof

The utility model discloses an addressing parallel display drive circuit including a receiving and decoding module, a display data processing module and an address data processing module. The receiving and decoding module is used for decoding receiving data, extracting display data and address data, and inputting the display data and address data to the display data processing module and the address data processing module. The display data processing module is used for outputting a drive signal according to the display data and controlling an LED display device. The address data processing module is used for receiving and storing the address data and transmitting and outputting the address data. The utility model also discloses a display control system. By using the scheme in the utility model, the address data can be input in a serial connection manner and the data input can be displayed in a parallel connection manner in a special parallel integrated circuit having a function of controlling an independent light fixture, thereby improving the production efficiency and the reliability of an LED display drive chip, reducing the cost of the display system and optimizing the system performance.